1. Field of the Invention
The present invention relates to electronics, and, in particular, to multi-step sub-ranging analog-to-digital converters.
2. Description of Related Art
FIG. 1 illustrates a block diagram of a conventional two-step sub-ranging analog-to-digital converter (ADC) 100. ADC 100 comprises a front-end Sample-and-Hold (S/H) module 101, a coarse converter 103, a fine converter 104, a reference ladder 105, a reference switch network 102, and an encoder 106. An analog input signal 111 is received by S/H module 101, which provides a stable input signal 112 for application to coarse converter module 103 and fine converter module 104.
Input signal 112 is converted by coarse converter 103 during a first phase of a conversion cycle based on a subset of reference voltages 113 provided by reference ladder 105. Coarse converter 103 generates one or more of the most significant bit (MSB) values (115) for the digital representation 117 of analog input signal 111. During a second phase of the conversion cycle, fine converter 104 converts input signal 112 to generate one or more of the least significant bit (LSB) values (116) for the digital representation of analog input signal 111. During this second phase, reference switch network 102 provides a different subset of reference voltages 114 to fine converter 104, where reference voltages 114 are selected based upon a control signal 120 generated by coarse converter 103 corresponding to the MSB values generated during the first phase of the conversion cycle. Encoder 117 combines the MSB values generated by coarse converter 103 and the LSB values generated by fine converter 104 to generate digital output signal 117.
Coarse converter 103 and fine converter 104 may be constructed using any suitable ADC circuits that provide the desired resolutions and accuracies. For example, in one possible embodiment, each converter is constructed using a set of analog comparators. Each of these comparators compares input signal 112 with a different reference voltage. Assume, for example, that ADC 100 generates an 8-bit digital output signal 117, where coarse converter 103 generates the four MSBs and fine converter 104 generates the four LSBs of output signal 117. In that case, reference ladder 105 generates 28−1 or 255 different (e.g., equally spaced) reference voltages that span the dynamic range of ADC 100. Assume, for ease of explanation, that the dynamic range of ADC 100 is from 0V to 256 mV, and that reference ladder 105 generates 255 reference voltages from 1 mV to 255 mV at 1-mV increments.
Continuing with this 8-bit ADC example, 4-bit coarse converter 103 and 4-bit fine converter 104 are both implemented with 15 comparators. During the first phase of the conversion cycle, coarse converter 103 receives 15 “coarse” reference voltages (e.g., corresponding to 16 mV, 32 mV, 48 mV, . . . , 240 mV), where each of the 15 comparators in coarse converter 103 compares input signal 112 to a different one of these 15 coarse reference voltages. The largest of these 15 coarse reference voltages that is smaller than input signal 112 (as determined by the comparator outputs) identifies the 4 MSBs of digital output 117. Assume, for example, that this “largest smaller” coarse reference voltage is 144 mV.
Coarse converter 103 generates control signal 120 based on this largest coarse reference voltage. Based on control signal 120, reference switch network 102 selects 15 “fine” reference voltages from the 255 different reference voltages 113 generated by reference ladder 105 to provide to fine converter 104. Continuing with the example in which the “largest smaller” coarse reference voltage is 144 mV, reference switch network 102 would select the following 15 fine reference voltages for use by fine converter 104: 145 mV, 146 mV, 147 mv, . . . , 159 mV. During the second phase of the conversion cycle, fine converter 104 receives the 15 selected fine reference voltages, where each of the 15 fine-converter comparators compares input signal 112 to a different one of these 15 fine reference voltages. The largest of these 15 fine reference voltages that is smaller than input signal 112 identifies the 4 LSBs of digital output 117.
FIG. 2 illustrates a signal flow diagram for one of the fine reference voltages selected by reference switch network 102 of FIG. 1 for use by fine converter 104 during the second phase of the conversion cycle. One of the design challenges of two-step sub-ranging ADC 100 of FIG. 1 is the settling accuracy of reference switch network 102 when changing fine reference voltages 114 for fine converter 104 for different input signals. This settling error has to be lower than a certain level for a specific resolution requirement of ADC 100. One major contributor to the settling error is a “memory effect” caused by electric charge stored at each reference input node 203 of fine converter 104. The memory effect occurs because of parasitic capacitance 205 between each output node of reference switch network 102 and the corresponding reference input node to fine converter 104. The reference settling process, and therefore the final settling accuracy, depends on the fine reference voltage levels of the previous conversion cycle stored on parasitic capacitances (205) at the interface between reference switch network 102 and the reference input nodes of fine converter 104.
For example, the settling error would be higher if the differences between the current fine reference voltages and the previous fine reference voltages become larger. In particular, because of the memory effect from parasitic capacitance 205, more time would be needed for the voltages at the reference input nodes of fine converter 104 to settle to the current fine reference voltages from the previous reference voltages. This memory effect causes an input-dependent settling error that lowers the observed Signal-to-Noise Ratio (SNR), and therefore the Effective Number of Bits (ENOB), of ADC 100. This problem becomes more severe in high-speed applications, where the input slew rate for analog input signal 111 of FIG. 1, and therefore the slew rate of reference switching network 102, is high and the time for reference switching is short. Other contributors to the reference settling error may include signal-dependent non-linearity and charge injection of the switch devices used in reference switch network 102.
Attempts to reduce these errors caused by the memory effect of the previous fine reference voltages stored at the reference input nodes of fine converter 104 include increasing driving current within reference ladder 105. This increase in the drive current attempts to lower the RC time constant of reference ladder 105, which drives reference switch network 102, and by lowering the resistance of switches within reference switch network 102. This approach increases the power consumption of ADC 100 and requires larger switch devices within reference switch network 102, which results in more charge injection.
Another previous attempt to reduce the reference settling error was to use two interleaved fine converters 104, each working at half the conversion rate of ADC 100. Although this architecture relaxes the time for the fine reference voltages to settle for each fine converter and therefore lowers the settling error, the addition of the second interleaved fine converter significantly increases the complexity of ADC 100, demands more die area for the entire circuit, and introduces errors caused by the interleaving operations, e.g., the “ping-pong” noise between the two fine converters.